This invention relates to a packaging technique suitable for implementing an electronic circuit in more than one package. It is contemplated that during initial design, design engineers will verify the correctness of their design by implementing the electronic circuit on a semi-custom mask programmable gate array commonly referred to as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs).
Due to increasing complexity in typical electronic circuits which require hundreds of input and output signals, such circuits are typically packaged in pin grid array (PGA) packages. Such packages may provide the hundreds of pins required for routing power and ground to the integrated circuit as well as input and output signal pins (I/O pins). For example, PGA packages are known in the art that provide about 565 power and I/O pins in area efficient packages that take up little space on a printed circuit board. This small footprint of the PGA packages permits more packages to be mounted on a printed circuit board, the length of signal lead and the capacitance associated with each lead on the printed circuit board can be minimized.
During design verification, it is highly desirable to design the printed circuit board such that the pattern of signal lines and power buss conductors on the printed circuit board conform to the final design pattern. However, it has been considered difficult, if not impossible, to implement an electronic circuit in an electrical system without one or more design iterations. As a consequence, one or more electronic circuits, which comprise the electrical system, are often implemented in ASICs or FPGAs which permit relatively easy design changes once an error has been detected. However, due to the inherent inefficiencies associated with implementing an electronic circuit in an ASIC or FPGA, multiple sub-circuits are often required to implement the electrical circuit intended for a single device package footprint. What is needed is a scheme for packaging multiple sub-circuits in individual package types while satisfying the stated constraint of not changing the footprint.